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LTC3675/LTC3675-1 1 36751fc for more information www.linear.com/LTC3675 typical a pplica t ion descrip t ion 7-channel configurable high power pmic the lt c ? 3675/LTC3675-1 are a digitally programmable high efficiency multioutput power supplies plus dual string led driver ics optimized for high power single cell li- ion/ polymer applications. the dc/ dcs consist of four synchronous buck converters (1a /1a /500ma/500ma), one synchronous boost dc / dc (1 a ), and one buck- boost dc/ dc (1a ) all powered from a 2.7 v to 5.5 v input. the 40v led driver can regulate up to 25ma of current through two led strings with up to 10 leds each. the led driver may also be configured as a general purpose high voltage boost converter. dc/dc enables, output voltages, switch slew rates and operating modes may all be independently programmed over i 2 c or used in standalone mode via simple i/o and power- up defaults. the buck dc / dc s may be used indepen- dently or paralleled to achieve higher output currents with a shared inductor. led enable , 60 db brightness control and up/down gradation are programmed using i 2 c. alarm levels for low v in and high die temperature may also be programmed via i 2 c with a maskable interrupt output to monitor dc / dc and system faults. pushbutton on/off/reset control and a power-on reset output provide flexible and reliable power-up sequencing. the LTC3675/LTC3675-1 are available in a low profile (0.75mm), thermally enhanced 44-lead 4mm 7mm qfn package. fea t ures a pplica t ions n four monolithic synchronous buck dc/dcs (1a/1a/500ma/500ma) n buck dc/dcs can be paralleled to deliver up to 2 current with a single inductor n independent 1a boost and 1a buck-boost dc/dcs n dual string i 2 c controlled 40v led driver n i 2 c programmable output voltage, operating mode, and switch node slew rate for all dc/dcs n i 2 c read back of dc/dc, led driver, fault status n i 2 c slave address options: LTC3675 = 0001001x, LTC3675-1 = 0110100x n maskable interrupts to report dc/dc, v in and die temperature faults n pushbutton on/off/reset n always-on 25ma ldo n low quiescent current: 16a (all dc/dcs off) n 4mm 7mm 0.75mm 44-lead qfn package n high power (5w to 10w) single cell li-ion/polymer applications n portable industrial applications, handy terminals, portable instruments n multioutput low v oltage power supplies l , lt , lt c , lt m , linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. LTC3675/ LTC3675-1 exposed pad 0.01f push button digital control 2.7v to 5.5v ? ? ? v in i 2 c en1 en2 en3 en4 enbb irqb rstb wake pbstat onb ct sw1 sw2 sw3 sw4 sw5 vout5 swab6 swcd6 vout6 ldo_out sw7 led1 led2 0.425v to v in , 1a max 0.425v to v in , 1a max 0.425v to v in , 500ma max 0.425v to v in , 500ma max v in v in to 5.35v, 1a max 2.65v to 5.25v, 1a max 0.8v to v in , 25ma max 36751 ta01 ? ? ? up to 10 leds per string v in 3
LTC3675/LTC3675-1 2 36751fc for more information www.linear.com/LTC3675 table o f c on t en t s features ............................................................................................................................ 1 applications ....................................................................................................................... 1 t ypical application ............................................................................................................... 1 description ......................................................................................................................... 1 absolute maximum ratings ..................................................................................................... 3 order information ................................................................................................................. 3 pin configuration ................................................................................................................. 3 electrical characteristics ........................................................................................................ 4 t ypical performance characteristics .......................................................................................... 8 pin functions ..................................................................................................................... 14 block diagram .................................................................................................................... 16 operation ..........................................................................................................................17 buck switching regulator .................................................................................................................................... 17 buck regulators with combined power stages .................................................................................................... 17 boost switching regulator ................................................................................................................................... 18 buck-boost switching regulator .......................................................................................................................... 18 led driver ............................................................................................................................... ............................. 18 pushbutton interface and power-up power-down sequencing ............................................................................ 19 power -up and power-down via pushbutton ......................................................................................................... 19 power-up and power -down via enable pin or i 2 c ................................................................................................. 21 led current programming ............................................................................................................................... .... 21 i 2 c interface .......................................................................................................................................................... 21 error condition reporting via rstb and irqb pins ............................................................................................................................... .............. 24 undervoltage and overtemperature functionality ................................................................................................. 25 applications information ....................................................................................................... 26 switching regulator output v oltage and feedback network................................................................................. 26 buck regulators ................................................................................................................................................... 26 combined buck regulators .................................................................................................................................. 26 boost regulator ............................................................................................................................... ..................... 27 buck-boost regulator ........................................................................................................................................... 28 led driver ............................................................................................................................... ............................. 28 operating the led driver as a high voltage boost regulator ............................................................................... 29 input and output decoupling capacitor selection ................................................................................................. 29 choosing the c t capacitor ................................................................................................................................... 30 programming the uvot register ......................................................................................................................... 30 programming the rstb and irqb mask registers .............................................................................................. 30 status byte read back ......................................................................................................................................... 31 pcb considerations .............................................................................................................................................. 31 t ypical applications ............................................................................................................. 33 package description ............................................................................................................ 36 revision history ................................................................................................................. 37 t ypical application .............................................................................................................. 38 related parts ..................................................................................................................... 38
LTC3675/LTC3675-1 3 36751fc for more information www.linear.com/LTC3675 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , v out 5 , v out 6 , fb 1-6, led _ ov , en 1-4, enbb , led _ fs , ct , wake , pbstat , irqb , rstb , onb , dv cc , sw5 ............................................. C 0.3 v to 6v ( static ) ldo _ out , ldofb ... C 0.3 v to lesser of ( v in + 0.3 v ) or 6 v scl , sda .......... C 0.3 v to lesser of ( dv cc + 0.3 v) or 6v sw 1, sw 2, sw 3, sw 4, swab 6 ........................ C 0.3 v to lesser of (v in + 0.3 v) or 6v swcd 6 ............ C 0.3 v to lesser of (v out 6 + 0.3 v) or 6v sw7 ........................................................... C0. 3 v to 45 v i sw 1 , i sw 2 ................................................................ 1.4 a i sw 3 , i sw 4 ............................................................ 700 ma i sw 5 , i swab 6 , i swcd 6 ................................................ 2.4 a i sw 7 ............................................................................ 2a op erating junction temperature range ( notes 2, 3) .......................................................... C 40 c to 125 c storage temperature range .................. C 65 c to 125 c (note 1) top view 45 gnd uff package 44-lead (7mm 4mm) plastic qfn en1 1 fb1 2 fb2 3 en2 4 sw1 5 v in 6 v in 7 sw2 8 sw3 9 v in 10 sw4 11 en3 12 en4 13 fb4 14 fb3 15 37 enbb 36 fb6 35 fb5 34 v in 33 v out5 32 sw5 31 v in 30 ldo_out 29 ldofb 28 onb 27 led_fs 26 wake 25 pbstat 24 irqb 23 rstb led_0v 16 led1 17 sw7 18 sw7 19 sw7 20 led2 21 ct 22 44 swcd6 43 sda 42 v out6 41 dv cc 40 v in 39 scl 38 swab6 t jmax = 125c, ja = 45c/w exposed pad (pin 45) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range LTC3675euff#pbf LTC3675euff#trpbf 3675 44-lead (7mm 4mm) plastic qfn C40c to 125c LTC3675euff-1#pbf LTC3675euff-1#trpbf 36751 44-lead (7mm 4mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC3675/LTC3675-1 4 36751fc for more information www.linear.com/LTC3675 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = 3.6v. (note 2) symbol parameter conditions min typ max units v in input supply range l 2.7 5.5 v v in_falling falling undervoltage threshold l 2.35 2.45 2.55 v v in_rising rising undervoltage threshold l 2.45 2.55 2.65 v v in_warn falling undervoltage warning threshold uv[2], uv[1], uv[0] = 000 2.7 v uv[2], uv[1], uv[0] = 001 2.8 v uv[2], uv[1], uv[0] = 010 2.9 v uv[2], uv[1], uv[0] = 011 3.0 v uv[2], uv[1], uv[0] = 100 3.1 v uv[2], uv[1], uv[0] = 101 3.2 v uv[2], uv[1], uv[0] = 110 3.3 v uv[2], uv[1], uv[0] = 111 3.4 v v in_hys v in undervoltage warning hysteresis 50 mv v in_warn(lsb) undervoltage warning threshold step size l 85 100 115 mv ot overtemperature shutdown 150 c ot_warn overtemperature warning threshold; die temperature below ot that causes irqb = 0 ot[1], ot[0] = 00 ot[1], ot[0] = 01 ot[1], ot[0] = 10 ot[1], ot[0] = 11 10 20 30 40 c c c c i vin_alloff input supply current all switching regulators and led driver in shutdown, onb = high; sum of all v in currents 16 28 a f osc voltage regulator switching frequency all voltage regulators l 1.8 2.25 2.7 mhz v pgood(fall) falling pgood threshold voltage full-scale (1,1,1,1) reference voltage l 88 92 96 % v pgood(hys) pgood hysteresis all regulators except led driver 1 % 1a buck regulator (buck regulators 1 and 2) i vin1,2 pulse-skipping input current burst mode ? operation input current v fb1 = v fb2 = 0.85v (notes 4, 5) v fb1 = v fb2 = 0.85v (notes 4, 5) 105 20 200 50 a a i fwd 1,2 pmos current limit (note 6) 2.25 2.8 3.35 a v fb1,2(high) feedback regulation voltage pulse-skipping mode full-scale (1,1,1,1) l 780 800 820 mv v fb1,2(low) feedback regulation voltage pulse-skipping mode full-scale (0,0,0,0) l 405 425 445 mv v lsb1,2 fb1, fb2 regulation voltage step size 25 mv i fb12 feedback leakage current v fb1 = v fb2 = 0.85v C50 50 na d max1,2 maximum duty cycle v fb1 = v fb2 = 0v l 100 % r pmos1,2 pmos on-resistance i sw1 = i sw2 = 100ma 265 m? r nmos1,2 nmos on-resistance i sw1 = i sw2 = C100ma 280 m? i leakp1,2 pmos leakage current en1 = en2 = 0 C2 2 a i leakn1,2 nmos leakage current en1 = en2 = 0 C2 2 a r swpd1,2 output pull-down resistance in shutdown en1 = en2 = 0 (i 2 c bit set) 10 k? t ss1,2 soft-start time 500 s 500ma buck regulator (buck regulators 3 and 4) i vin3,4 pulse-skipping input current burst mode operation input current v fb3 = v fb4 = 0.85v (notes 4, 5) v fb3 = v fb4 = 0.85v (notes 4, 5) 105 20 200 50 a a i fwd 3,4 pmos current limit (note 6) 0.75 1.2 1.65 a
LTC3675/LTC3675-1 5 36751fc for more information www.linear.com/LTC3675 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = 3.6v. (note 2) symbol parameter conditions min typ max units v fb3,4(high) feedback regulation voltage pulse-skipping mode full-scale (1,1,1,1) l 780 800 820 mv v fb3,4(low) feedback regulation voltage pulse-skipping mode full-scale (0,0,0,0) l 405 425 445 mv v lsb3,4 fb3, fb4 regulation voltage step size 25 mv i fb3,4 feedback leakage current v fb3 = v fb4 = 0.85v C50 50 na d max 3,4 maximum duty cycle v fb3 = v fb4 = 0v l 100 % r pmos3,4 pmos on-resistance i sw3 = i sw4 = 100ma 500 m r nmos3,4 nmos on-resistance i sw3 = i sw4 = C100ma 510 m i leakp3,4 pmos leakage current en3 = en4 = 0 C1 1 a i leakn3,4 nmos leakage current en3 = en4 = 0 C1 1 a r swpd3,4 output pull-down resistance in shutdown en3 = en4 = 0 (i 2 c bit set) 10 k t ss3,4 soft-start time 500 s buck regulators combined i fwd 1+2 pmos current limit fb2 = v in (note 6) 5.6 a i fwd 2+3 pmos current limit fb3 = v in (note 6) 4 a i fwd 3+4 pmos current limit fb4 = v in (note 6) 2.4 a 1a boost regulator i vin5 pwm mode burst mode operation v fb5 = 0.85v (notes 4, 5) v fb5 = 0.85v (notes 4, 5) 150 35 300 60 a a v out5(max) maximum regulated output voltage 5.35 5.55 5.75 v i fwd 5 forward current limit (note 6) 2.5 3.15 3.9 a v fb5(high) feedback regulation voltage pwm mode full-scale (1,1,1,1) l 780 800 820 mv v fb5(low) feedback regulation voltage pwm mode full-scale (0,0,0,0) l 405 425 445 mv v lsb5 fb5 regulation voltage step size 25 mv i fb5 feedback leakage current v fb5 = 0.85v C50 50 na dc max 5 maximum duty cycle nmos switch 90 % r pmos5 pmos on-resistance 260 m r nmos5 nmos on-resistance 275 m i leakp pmos switch leakage current C2 2 a i leakn nmos switch leakage current C2 2 a r outpd5 output pull-down resistance in shutdown boost regulator off 10 k t ss5 soft-start time 500 s 1a buck-boost regulator i vin6 pwm mode burst mode operation v fb6 = 0.85v (note 4, 5) v fb6 = 0.85v(note 4, 5) 220 20 400 40 a a v out6( low ) minimum regulated output voltage 2.65 2.8 v v out6( high ) maximum regulated output voltage 5.25 5.65 v i fwd 6 forward current limit pwm mode (note 6) 2.1 2.65 3.2 a i peak6 peak current limit burst mode operation (note 6) 200 275 350 ma i zero6 zero current limit burst mode operation C30 0 30 ma v fb6(high) feedback regulation voltage pwm mode full-scale (1,1,1,1) l 780 800 820 mv v fb6(low) feedback regulation voltage pwm mode full-scale (0,0,0,0) l 405 425 445 mv v lsb6 fb6 regulation voltage step size 25 mv
LTC3675/LTC3675-1 6 36751fc for more information www.linear.com/LTC3675 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = 3.6v. (note 2) symbol parameter conditions min typ max units i fb6 feedback leakage current v fb6 = 0.85v C50 50 na dc6 buck ( max ) maximum buck duty cycle duty cycle of pmos switch a l 100 % dc6 boost ( max ) maximum boost duty cycle duty cycle of nmos switch c 75 % r pmos6 pmos on-resistance switches a and d 260 m? r nmos6 nmos on-resistance switches b and c 275 m? i leakp pmos switch leakage current C2 2 a i leakn nmos switch leakage current C2 2 a t ss soft-start time 500 s r outpd6 output pull-down resistance in shutdown enbb = 0 10 k led driver; r led_fs = 20k? i vin7 input current (mode0 = mode1 = 0) led_ov = 0.85v (notes 4, 5) 700 1000 a v led_ov led overvoltage threshold feedback voltage operating in led mode operating in boost mode l l 805 770 825 800 845 830 mv mv v led_fs led full-scale voltage l 775 800 825 mv v led1,2 led pin regulation voltage (note 7) 300 mv v led1,2_clmp led regulation voltage clamp l 6.0 8.3 v i lim7 maximum current limit (note 6) 1.6 1.85 2.15 a i led_fs led full-scale current l 23.25 25.0 26.75 ma i led_2fs led full current high current mode l 46.5 50 53.5 ma i led_match led1 and led2 current matching at full-scale |i led1 ? i led2 | i led1 + i led2 2 ? ? ? ? ? ? ? 100 l 1 % i led_lsb led current lsb 98 a r nmos7 nmos on-resistance 300 m i leak_nmos7 nmos switch leakage v sw7 = 5.5v C1 1 a f ledosc oscillator frequency l 450 562.5 675 khz dc max7 maximum duty cycle nmos switch 97 % 25ma always-on ldo v ldofb feedback regulation voltage l 780 800 820 mv r do dropout resistance 12 i 2 c port dv cc input supply voltage l 1.6 5.5 v i dvcc input supply current scl/sda= 0khz 0.3 1 a dv cc_uvlo dv cc uvlo 1 v address i 2 c address LTC3675 LTC3675-1 l l 0001001[r/wb] 0110100[r/wb] v ih input high voltage sda/scl 70 %dv cc v il input low voltage sda/scl 30 %dv cc i ih input high current sda/scl C1 0 1 a i il input low current sda/scl C1 0 1 a v ol_sda sda output low voltage i sda = 3ma 0.4 v f scl clock operating frequency 400 khz
LTC3675/LTC3675-1 7 36751fc for more information www.linear.com/LTC3675 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = 3.6v. (note 2) symbol parameter conditions min typ max units t buf bus free time between stop and start condition 1.3 s t hd_sda hold time after repeated start condition 0.6 s t su_ sta repeated start condition set-up time 0.6 s t su_sto stop condition set-up time 0.6 s t hd_ dat (o) data hold time output 0 900 ns t hd_ dat (i) data hold time input 0 ns t su_ dat data set-up time 100 ns t low scl clock low period 1.3 s t high scl clock high period 0.6 s t f clock/data fall time c b = capacitance of one bus line (pf) 2 0+ 0.1c b 300 ns t r clock/data rise time c b = capacitance of one bus line (pf) 2 0+ 0.1c b 300 ns t sp input spike suppression pulse width 50 ns interface logic pins (pbstat, wake, rstb, irqb, onb) i lk(high) output high leakage current 3.6v at pin C1 1 a v ol output low voltage 3ma into pin 100 400 mv v onb(high) onb high threshold 800 1200 mv v onb(low) onb low threshold 400 700 mv interface logic pins (en1, en2, en3, en4, enbb) v hi_alloff enable rising threshold all regulators and led driver disabled l 400 650 1200 mv v en_hys enable falling hysteresis 60 mv v hi enable rising threshold at least one regulator/led driver enabled l 380 400 420 mv i en enable pin leakage current en = 3.6v C1 1 a pushbutton parameters; ct = 0.01f t onb_lo onb low time to pbstat low wake high 28 50 72 ms t onb_wake onb low time to wake high 280 400 520 ms t onb_hr onb low to hard reset 3.5 5 6.5 sec t hr time for which all enabled regulators are disabled 0.7 1 1.3 sec t pbstat_pw pbstat minimum pulse width 28 50 72 ms t wake_on wake high time 3.5 5 6.5 sec note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3675/LTC3675-1 are tested under pulsed load conditions such that t a t j . the LTC3675/ LTC3675-1 are guaranteed to meet performance specifications from 0 c to 125c . specifications over the C40 c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: the LTC3675/LTC3675-1 include overtemperature protection which protects the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 4: static current, switches not switching. actual current may be higher due to gate charge losses at the switching frequency. note 5: currents measured at a specific v in pin. buck 1 (v in , pin 6); buck 2 (v in , pin 7); buck 3 and buck 4 (v in , pin 10); boost and buck boost (v in , pin 34); led driver (v in , pin 31). note 6: the current limit features of this part are intended to protect the ic from short term or intermittent fault conditions. continuous operation above the maximum specified pin current rating may result in device degradation over time. note 7: with dual string operation, the led pin with the lower voltage sets the regulation point.
LTC3675/LTC3675-1 8 36751fc for more information www.linear.com/LTC3675 typical p er f or m ance c harac t eris t ics enable threshold vs temperature enable pin precision threshold vs temperature 1a buck regulators, efficiency vs load 1a buck regulators, efficiency vs load 1a buck regulators, load regulation 1a buck regulators, line regulation undervoltage threshold vs temperature input supply current vs temperature oscillator frequency vs temperature t a = 25c, unless otherwise noted. temperature (c) uv threshold (v) 2.70 2.60 2.65 2.45 2.40 2.55 2.50 2.35 2.30 ?15?35 36751 g01 5 25 65 85 105 125 ?55 45 v in_falling v in_rising temperature (c) i vin_alloff (a) 50 40 45 30 35 15 10 25 20 5 0 ?15?35 36751 g02 5 25 65 85 105 125 ?55 45 v in = 2.7v v in = 3.6v v in = 5.5v all regulators and led driver in shutdown temperature (c) f osc (mhz) 2.50 2.40 2.45 2.30 2.35 2.15 2.10 2.25 2.20 2.05 2.00 ?15?35 36751 g03 5 25 65 85 105 125 ?55 45 v in = 2.7v v in = 3.6v v in = 5.5v temperature (c) en threshold (v) 900 800 850 700 750 550 650 600 450 500 400 ?15?35 36751 g04 5 25 65 85 105 125 ?55 45 en rising en falling all regulators and led driver disabled, v in = 3.6v temperature (c) en threshold (mv) 420 410 415 400 405 385 395 390 380 ?15?35 36751 g05 5 25 65 85 105 125 ?55 45 en rising threshold measured with a regulator enabled, v in = 3.6v en falling load current (ma) efficiency (%) 100 60 70 80 90 40 50 10 30 20 0 36751 g06 10 100 1000 1 v in = 2.7v burst mode operation v in = 3.6v burst mode operation v in = 5.5v burst mode operation v in = 2.7v pulse skipping-mode v in = 3.6v pulse skipping-mode v in = 5.5v pulse skipping-mode v out = 1.2v load current (ma) efficiency (%) 100 60 70 80 90 40 50 10 30 20 0 36751 g07 10 100 1000 1 v in = 2.7v burst mode operation v in = 3.6v burst mode operation v in = 5.5v burst mode operation v in = 2.7v pulse skipping-mode v in = 3.6v pulse skipping-mode v in = 5.5v pulse skipping-mode v out = 2.5v load current (ma) v out1 (v) 1.220 1.204 1.208 1.212 1.216 1.196 1.200 1.184 1.192 1.188 1.180 36751 g08 10 100 1000 1 v in = 2.7v pulse-skipping mode v in = 3.6v v in = 5.5v v in (v) v out1 (v) 1.220 1.212 1.196 1.188 1.204 1.180 1.216 1.200 1.192 1.208 1.184 36751 g09 3.1 5.14.7 5.5 3.93.5 4.3 2.7 pulse-skipping mode load = 100ma load = 500ma
LTC3675/LTC3675-1 9 36751fc for more information www.linear.com/LTC3675 typical p er f or m ance c harac t eris t ics 1a buck regulators, v out1 vs temperature 1a buck regulators, pmos current limit vs temperature 1a buck regulators, switch r dson vs temperature 500ma buck regulators, efficiency vs load 500ma buck regulators, load regulation 500ma buck regulators, line regulation 1a buck regulators, transient response (pulse-skipping mode) 1a buck regulators, transient response (burst mode operation) 1a buck regulators, no load start-up transient (pulse-skipping mode) t a = 25c, unless otherwise noted. 50s/div v out1 100mv/div ac-coupled inductor current 200ma/div 0ma load step = 100ma to 700ma v in = 3.6v, v out1 = 1.2v 36751 g10 50s/div v out1 100mv/div ac-coupled inductor current 200ma/div 0ma 36751 g11 load step = 100ma to 700ma v in = 3.6v, v out1 = 1.2v 25s/div v out1 500mv/div inductor current 500ma/div en1 2v/div 36751 g12 v in = 3.6v temperature (c) v out1 (v) 1.25 1.23 1.24 1.21 1.22 1.18 1.17 1.20 1.19 1.16 1.15 ?15?35 36751 g13 5 25 65 85 105 125 ?55 45 v in = 3.6v v in = 5.5v v in = 2.7v pulse-skipping mode load = 500ma temperature (c) i fwd1, 2 (a) 3.6 3.2 3.4 2.8 3.0 2.2 2.0 2.6 2.4 1.8 1.6 ?15?35 36751 g14 5 25 65 85 105 125 ?55 45 v in = 3.6v v in = 5.5v v in = 2.7v temperature (c) r dson () 0.60 0.50 0.55 0.40 0.45 0.25 0.20 0.35 0.30 0.15 0.10 0.05 0 ?15?35 36751 g15 5 25 65 85 105 125 ?55 45 nmos r dson , v in = 5.5v nmos r dson , v in = 2.7v pmos r dson , v in = 5.5v pmos r dson , v in = 2.7v load current (ma) efficiency (%) 100 80 90 60 70 30 20 50 40 10 0 10 36751 g16 1000 1 100 v in = 2.7v burst mode operation v in = 3.6v burst mode operation v in = 5.5v burst mode operation v in = 2.7v pulse skipping-mode v in = 3.6v pulse skipping-mode v in = 5.5v pulse skipping-mode v out3 = 1.8v load current (ma) v out3 (v) 1.830 1.820 1.825 1.810 1.815 1.795 1.790 1.805 1.800 1.785 1.780 1.775 1.770 100 10 36751 g17 1000 1 v in = 5.5v v in = 2.7v pulse-skipping mode v in = 3.6v v in (v) v out3 (v) 1.830 1.810 1.820 1.825 1.815 1.790 1.800 1.805 1.770 1.795 1.785 1.780 1.775 3.53.1 36751 g18 3.9 4.3 5.1 5.5 2.7 4.7 load = 250ma pulse-skipping mode load = 50ma
LTC3675/LTC3675-1 10 36751fc for more information www.linear.com/LTC3675 typical p er f or m ance c harac t eris t ics 500ma buck regulators, v out3 vs temperature 500ma buck regulators, pmos current limit vs temperature 500ma buck regulators, switch r dson vs temperature ganged buck regulators 1 and 2, efficiency vs load boost regulator, efficiency vs load boost regulator, load regulation 500ma buck regulators transient response (pulse-skipping mode) 500ma buck regulators transient response (burst mode operation) 500ma buck regulators no load start-up transient (pulse-skipping mode) t a = 25c, unless otherwise noted. 50s/div v out3 100mv/div ac-coupled inductor current 100ma/div load step = 50ma to 300ma v in = 3.6v, v out3 = 1.8v 36751 g19 50s/div v out3 100mv/div ac-coupled inductor current 100ma/div load step = 50ma to 300ma v in = 3.6v, v out3 = 1.8v 36751 g20 25s/div v out3 500mv/div inductor current 500ma/div en 2v/div 36751 g21 v in = 3.6v temperature (c) v out3 (v) 1.90 1.86 1.88 1.82 1.84 1.76 1.74 1.80 1.78 1.72 1.70 ?15?35 36751 g22 5 25 65 85 105 125 ?55 45 v in = 2.7v pulse-skipping mode, load = 250ma v in = 3.6v v in = 5.5v temperature (c) i fwd3,4 (a) 1.50 1.30 1.35 1.40 1.45 1.20 1.25 1.05 1.00 1.15 1.10 0.95 0.90 ?15?35 36751 g23 5 25 65 85 105 125 ?55 45 v in = 2.7v v in = 3.6v v in = 5.5v temperature (c) r dson () 1.0 0.8 0.9 0.6 0.7 0.3 0.2 0.5 0.4 0.1 0 ?15?35 36751 g24 5 25 65 85 105 125 ?55 45 nmos r dson , v in = 2.7v pmos r dson , v in = 2.7v pmos r dson , v in = 5.5v nmos r dson , v in = 5.5v load current (ma) efficiency (%) 100 90 95 80 85 65 50 75 70 45 60 55 40 100 10 36751 g25 1000 10000 1 pulse-skipping mode burst mode operation v in = 3.6v, v out1 = 1.2v load current (ma) efficiency (%) 100 90 80 50 20 70 60 10 40 30 0 100 10 36751 g26 1000 1 v in = 2.7v burst mode operation v in = 3.6v burst mode operation v in = 1.2v burst mode operation v in = 2.7v pwm mode v in = 3.6v pwm mode v in = 4.2v pwm mode v out5 = 5v load current (ma) v out5 (v) 5.20 5.05 4.90 5.15 5.10 4.85 5.00 4.95 4.80 100 10 36751 g27 1000 1 pwm mode v in = 4.2v v in = 2.7v v in = 3.6v
LTC3675/LTC3675-1 11 36751fc for more information www.linear.com/LTC3675 typical p er f or m ance c harac t eris t ics boost regulator, no load start-up transient, pwm mode boost regulator, v out5 vs temperature boost regulator, forward current limit vs temperature boost regulator, line regulation boost regulator transient response ( pwm mode) boost regulator transient response (burst mode operation) v in (v) v out5 (v) 5.020 5.012 5.016 5.004 5.008 4.992 4.988 5.000 4.996 4.984 4.980 36751 g28 3.1 3.5 4.3 4.7 5.1 5.5 2.7 3.9 load = 500ma load = 100ma pwm mode 200s/div v out5 100mv/div ac-coupled inductor current 200ma/div load step = 100ma to 600ma v in = 3.6v, v out5 = 5v 36751 g29 50s/div v out5 100mv/div ac-coupled inductor current 500ma/div 0ma 36751 g30 load step = 100ma to 600ma v in = 3.6v, v out5 = 5v 50s/div v out5 2v/div inductor current 500ma/div 36751 g31 v in = 3.6v temperature (c) v out5 (v) 5.10 5.06 5.08 5.02 5.04 4.96 4.94 5.00 4.98 4.92 4.90 ?15?35 36751 g32 5 25 65 85 105 125 ?55 45 v in = 2.7v pwm mode, load = 500ma v in = 3.6v v in = 4.2v temperature (c) i fwd5 (a) 3.50 3.30 3.40 3.10 3.20 3.00 2.90 2.80 3.35 3.45 3.15 3.25 3.05 2.95 2.85 ?15?35 36751 g33 5 25 65 85 105 125 ?55 45 v in = 2.7v v in = 4.2v v in = 3.6v
LTC3675/LTC3675-1 12 36751fc for more information www.linear.com/LTC3675 typical p er f or m ance c harac t eris t ics buck-boost regulator transient response ( pwm mode) buck-boost regulator no load start-up ( pwm mode) buck-boost regulator, reduction in load current deliverability buck-boost regulator, efficiency vs load buck-boost regulator, load regulation buck-boost regulator, line regulation load current (ma) efficiency (%) 100 80 90 60 70 30 20 50 40 10 0 36751 g34 10 100 1000 1 v in = 2.7v v in = 5.5v v in = 3.6v burst mode operation pwm mode load current (ma) v out6 (v) 3.35 3.33 3.34 3.31 3.32 3.28 3.27 3.30 3.29 3.26 3.25 100 10 36751 g35 1000 1 v in = 4.2v v in = 2.7v v in = 3.6v pwm mode v in (v) v out6 (v) 3.40 3.36 3.38 3.32 3.34 3.26 3.24 3.30 3.28 3.22 3.20 5.1 3.1 3.5 3.9 4.3 4.7 36751 g36 5.5 2.7 pwm mode load = 100ma load = 500ma 200s/div v out6 200mv/div ac-coupled inductor current 200ma/div load step = 100ma to 600ma v in = 3.6v, v out6 = 3.3v 36751 g37 100s/div v out6 1v/div inductor current 500ma/div en6 2v/div 36751 g38 v in = 3.6v v in (v) reduction below 1a (ma) 400 300 350 200 250 50 150 100 0 3 3.3 3.6 3.9 36751 g39 4.2 2.7 pwm mode v out6 = 3.3v
LTC3675/LTC3675-1 13 36751fc for more information www.linear.com/LTC3675 typical p er f or m ance c harac t eris t ics led driver, led current vs temperature high voltage boost regulator, efficiency vs load always-on ldo, load regulation buck-boost regulator, v out6 vs temperature buck-boost regulator, forward current limit vs temperature buck-boost regulator, switch r dson vs temperature led driver, dual string efficiency, 10 leds per string led driver, dual string efficiency, 4 leds per string led driver, forward current limit vs temperature temperature (c) v out6 (v) 3.40 3.36 3.38 3.32 3.34 3.26 3.24 3.30 3.28 3.22 3.20 ?15?35 36751 g40 5 25 65 85 105 125 ?55 45 v in = 2.7v v in = 3.6v v in = 5.5v pwm mode, load = 500ma temperature (c) i fwd6 (a) 2.90 2.80 2.85 2.70 2.75 2.55 2.50 2.65 2.60 2.45 2.40 ?15?35 36751 g41 5 25 65 85 105 125 ?55 45 v in = 2.7v v in = 3.6v v in = 4.2v temperature (c) r dson () 0.60 0.50 0.55 0.40 0.45 0.25 0.20 0.35 0.30 0.15 0.10 0.05 0 ?15?35 36751 g42 5 25 65 85 105 125 ?55 45 nmos r dson , v in = 2.7v pmos r dson , v in = 2.7v pmos r dson , v in = 4.2v nmos r dson , v in = 4.2v dac code (decimal) efficiency (%) 100 80 90 60 70 30 20 50 40 10 0 100 10 36751 g43 1000 1 v in = 4.2v v in = 2.7v r led_fs = 20k dac code (decimal) efficiency (%) 100 80 90 60 70 30 20 50 40 10 0 100 10 36751 g44 1000 1 v in = 4.2v v in = 2.7v r led_fs = 20k temperature (c) i fwd6 (a) 2.10 2.00 2.05 1.85 1.80 1.95 1.90 1.75 1.70 1.65 1.60 ?15?35 36751 g45 5 25 65 85 105 125 ?55 45 v in = 3.6v v in = 2.7v v in = 5.5v temperature (c) i led (ma) 10.25 10.15 10.20 10.00 9.95 10.10 10.05 9.90 9.85 9.80 9.75 ?15?35 36751 g46 5 25 65 85 105 125 ?55 45 v in = 5.5v v in = 2.7v v in = 3.6v single led string current mode0 = mode1 = 0 load current (ma) efficiency (%) 100 80 90 60 70 30 20 50 40 10 0 100 10 36751 g47 1000 1 v in = 2.7v v in = 3.6v v in = 5.5v mode1 = 1, mode0 = 0 v out = 12v load current (ma) v out (v) 1.220 1.210 1.215 1.195 1.190 1.205 1.200 1.185 1.180 10 1 36751 g48 100 0.1 v in = 2.7v v in = 5.5v v in = 3.6v
LTC3675/LTC3675-1 14 36751fc for more information www.linear.com/LTC3675 p in func t ions en 1 (pin 1): buck regulator 1 enable input. active high. this pin is a high impedance input; do not float. fb1 (pin 2): buck regulator 1 feedback pin. receives feedback by a resistor divider connected across the output. fb2 (pin 3): buck regulator 2 feedback pin. receives feedback by a resistor divider connected across the output. connecting fb2 to v in combines buck regulator 2 with buck regulator 1 for higher current. en 2 (pin 4): buck regulator 2 enable input. active high. this pin is a high impedance input; do not float. sw1 (pin 5): buck regulator 1 switch node. external inductor connects to this pin. v in (pin 6): buck regulator 1 input supply. a 10 f de- coupling capacitor to gnd is recommended. must be con- nected to all other v in supply pins (pins 7, 10, 31, 34, 40). v in (pin 7): buck regulator 2 input supply. a 10 f de- coupling capacitor to gnd is recommended. must be con- nected to all other v in supply pins (pins 6, 10, 31, 34, 40). sw2 (pin 8): buck regulator 2 switch node. external inductor connects to this pin. sw3 (pin 9): buck regulator 3 switch node. external inductor connects to this pin. v in (pin 10): buck regulators 3 and 4 input supply. a 10f decoupling capacitor to gnd is recommended. must be connected to all other v in supply pins (pins 6, 7, 31, 34, 40). sw4 (pin 11): buck regulator 4 switch node. external inductor connects to this pin. en3 (pin 12): buck regulator 3 enable input. active high. this pin is a high impedance input; do not float. en4 (pin 13): buck regulator 4 enable input. active high. this pin is a high impedance input; do not float. fb4 (pin 14): buck regulator 4 feedback pin. receives feedback by a resistor divider connected across the output. connecting fb4 to v in combines buck regulator 4 with buck regulator 3 for higher current. fb3 (pin 15): buck regulator 3 feedback pin. receives feedback by a resistor divider connected across the output. connecting fb3 to v in combines buck regulator 3 with buck regulator 2 for higher current. led_ov (pin 16): overvoltage protection pin for led driver. led1 (pin 17): connect a string of up to 10 leds to this pin. sw7 (pins 18, 19, 20): led driver switch node. external inductor connects to these pins. led2 (pin 21): connect a string of up to 10 leds to this pin. ct (pin 22): timing capacitor pin. a capacitor connected to gnd sets a time constant which is scaled for use by the wake, rstb and irqb pins. rstb (pin 23): reset pin. open drain output. when the regulated output voltage of a ny enabled switching regulator is more than 8% below its programmed level, this pin is driven low. assertion delay is scaled by the c t capacitor. irqb (pin 24): interrupt pin. open drain output. when undervoltage, overtemperature, or an unmasked error condition is detected, this pin is driven low. pbstat (pin 25): pushbutton status pin. open drain output. this pin provides a debounced and glitch free status of the onb pin.
LTC3675/LTC3675-1 15 36751fc for more information www.linear.com/LTC3675 p in func t ions wake (pin 26): open drain output. when the onb pin is pressed and released, the signal is debounced and the wake signal is held high for a minimum time period that is scaled by the c t capacitor. led_fs (pin 27): a resistor connected from this pin to gnd programs full-scale led current. onb (pin 28): pushbutton input. active low. ldofb (pin 29): ldo feedback pin. a resistor divider from ldo_out to gnd provides feedback. ldo_out (pin 30): output of always-on ldo. decouple with a 10f capacitor to gnd. v in (pin 31): quiet input supply used to power non- switching control circuitry. a 2.2 f decoupling capacitor to gnd is recommended. must be connected to all other v in supply pins (pins 6, 7, 10, 34, 40). sw 5 (pin 32): boost regulator switch node. external inductor connects to this pin. v out5 (pin 33): boost regulator output. connect two 22f capacitors to gnd. v in (pin 34): quiet input supply used to power non- switching control circuitry. a 2.2 f decoupling capacitor to gnd is recommended. must be connected to all other v in supply pins (pins 6, 7, 10, 31, 40). fb5 (pin 35): boost regulator feedback pin. receives feedback by a resistor divider connected across the output. fb6 ( pin 36): buck - boost regulator feedback pin. receives feedback by a resistor divider connected across the output. enbb (pin 37): buck-boost regulator enable input. ac- tive high. this pin is a high impedance input; do not float. swab 6 (pin 38): buck-boost regulator switch pin. ex- ternal inductor connects to this pin and swcd6. scl (pin 39): clock line for i 2 c port. v in (pin 40): buck-boost regulator input supply. a 10f decoupling capacitor to gnd is recommended. must be connected to all other v in supply pins ( pins 6, 7, 10, 31, 34). dv cc (pin 41): supply pin for i 2 c port. v out6 (pins 42): buck-boost regulator output. connect a 22f capacitor to gnd. sda (pin 43): serial data line for i 2 c port. open drain output during readback. swcd6 (pin 44): buck-boost regulator switch pin. ex- ternal inductor connects to this pin and swab6. gnd ( exposed pad pin 45): ground for entire chip. must be soldered to pcb for electrical contact and rated thermal performance.
LTC3675/LTC3675-1 16 36751fc for more information www.linear.com/LTC3675 b lock diagra m buck regulator 1 1a buck regulator 2 1a buck regulator 3 500ma buck regulator 4 500ma boost regulator ldo led driver buck-boost regulator ref, clk top logic, ct oscillator, timing gnd i 2 c v in v in modulation control modulation control bandgap, oscillator, uv, ot + ? v out5 sw5 fb5 v in swab6 swcd6 v out6 fb6 a b d c enbb led1 led2 led_fs led_ov v in ldo_out ldofb sw7 dv cc scl sda rstb irqb pbstat wake ct onb 36751 bd v in sw1 fb1 en1 v in master/slave lines master/slave lines master/slave lines sw2 fb2 en2 sw3 fb3 en3 v in sw4 fb4 en4 dac bits, slew control, gradation, status bits 6 5 2 33 40 42 37 32 35 1 7 8 3 4 9 15 12 10 11 14 13 44 38 36 18,19, 20 17 21 43 23 28 24 25 26 22 41 39 16 31 v in 34 27 29 30 45 v in
LTC3675/LTC3675-1 17 36751fc for more information www.linear.com/LTC3675 o pera t ion the LTC3675/ LTC3675-1 have six monolithic synchronous switching regulators and a dual string boost led driver and is designed to operate from a single li- ion battery. all of the switching regulators and the led driver are internally compensated and need only external feedback resistors for regulation. the switching regulators also offer two operat- ing modes: burst mode operation for higher efficiency at light loads and pulse- skipping/ pwm mode. in burst mode operation at light loads, the output capacitor is charged to a voltage slightly higher than its regulation point. the regulator then goes into sleep, during which the output capacitor provides the load current. in sleep most of the regulator s circuitry is powered down, helping conserve battery power. when the output capacitor droops below its programmed value, the circuitry is powered on and another burst cycle begins. the sleep time decreases as load current increases. all switching regulators and led driver may be configured via i 2 c, providing the user with the flexibility to operate the LTC3675/LTC3675-1 in the most efficient manner. i 2 c commands can also be read back via the i 2 c port, to ensure a command was not corrupted during a transmission. all the regulators can be enabled via i 2 c commands. the buck regulators and the buck-boost regulator may also be enabled via enable pins. the enable pins have two different enable threshold voltages that depend on the operating state of the LTC3675/LTC3675-1. with all regulators disabled, the enable pin threshold is at 650 mv. if any regulator is enabled either by its enable pin or an i 2 c command, then the enable pin thresholds are at 400 mv. a precision comparator detects a voltage greater than 400 mv on the enable pin and turns that regulator on. this precision threshold may be used to sequentially enable regulators. if all regulators are disabled, all the command registers are set in their default state. there are also 2 bytes of data that report any fault condi- tions on the LTC3675/LTC3675-1 via i 2 c read back. b uck s witching r egula tor the LTC3675/LTC3675-1 contain four buck regulators. tw o of the buck regulators are designed to deliver up to 1a load current each while the other two regulators can deliver up to 500ma each. the buck regulators can operate in either of two modes. in pulse-skipping mode, the regulator will skip pulses at light loads but will operate at a constant frequency of 2.25mhz at higher loads. in burst mode operation, the regulator will burst at light loads whereas at higher loads it will operate at constant frequency pwm mode of operation, much the same as pulse-skipping mode at high load. in shutdown, an i 2 c control bit provides the flexibility to either keep the sw node in a high impedance state or pull the sw node to gnd through a 10k resistor. the buck regulators have forward and reverse current limiting, soft-start to limit inrush current during start-up, short-circuit protection and slew rate control for lower radiated emi. each buck regulator may be enabled via its enable pin or i 2 c. the mode of operation, the feedback regulation volt- age and switch slew rate can all be controlled via i 2 c. for applications that require higher power, buck regulators may be combined together. b uck r egula tors with c ombined p ower s t ages tw o adjacent buck regulators may be combined in a master-slave configuration by connecting their sw pins together and connecting the higher numbered bucks fb pin to the input supply. the lower numbered buck is always the master. the higher numbered buck is a slave and its enable pin must be tied to ground. in figure 1, buck figure 1. buck regulators configured as master-slave buck regulator 1 (master) v in v in sw1 c out 1.2v 2a v out 400k l1 800k fb1 en1 buck regulator 2 (slave) v in sw2 en2 fb2 36751 f01
LTC3675/LTC3675-1 18 36751fc for more information www.linear.com/LTC3675 o pera t ion regulator 1 is the master. the feedback network connected to the fb1 pin programs the output voltage to 1.2 v. the fb2 pin is tied to v in , which configures buck regulator 2 as the slave. the sw1 and sw2 pins must be tied together. the register contents of the master program the combined buck regulators behavior and the register contents of the slave are ignored. the slave buck control circuitry draws no current. the enable of the master buck ( en1) controls the operation of the combined bucks. buck regulators 2 and 3 may be configured as combined buck regulators capable of delivering up to 1.5 a load current with buck regulator 2 being the master. buck regulators 3 and 4 may be configured as combined buck regulators capable of delivering up to 1 a load current with buck regulator 3 being the master. b oost s witching r egula tor the boost regulator is capable of delivering up to 1 a load current for a programmed output voltage of up to 5 v. the boost regulator may be enabled only via i 2 c. the mode of operation, feedback regulation voltage and switch slew rate can all be controlled via i 2 c. the boost regulator can operate in either pwm mode or in burst mode operation. in pw m operating mode, the regulator operates at a constant frequency of 2.25mhz and provides a low noise solution. for light loads, burst mode operation offers improved efficiency. the boost regulator has forward and reverse current limiting, soft- start to limit inrush current during start-up, short-circuit protection and slew rate control for lower radiated emi. the boost regulator also features true output disconnect when in shutdown. in shutdown, an internal 10 k resistor pulls the output to gnd. b uck -b oost s witching r egula tor the buck-boost regulator is a 2.25 mhz voltage mode regulator. the buck- boost regulator is capable of delivering up to 1 a load current for a programmed output voltage of 3.3 v. the regulator can be enabled via its enable pin or via i 2 c. the mode of operation, feedback regulation voltage and switch slew rate can all be controlled via i 2 c. the buck-boost regulator can operate in either pwm mode or in burst mode operation. the pwm operating mode provides a low noise solution. for light loads, burst mode operation offers improved efficiency. the buck - boost regulator has forward current limiting, soft-start to limit inrush current during start-up, short-circuit protection and slew rate control for lower radiated emi. when the output voltage is below 2.65v ( typical) during start-up, burst mode operation is disabled and switch d is turned off. the forward current is carried by the switch d well diode and there is no reverse current flowing in this condition. in shutdown, an internal 10 k resistor pulls the output to gnd. led d river the led driver uses a constant frequency, current mode boost converter to supply power to up to two strings of 10 series leds. the series string of leds is connected from the output of the boost converter to an led pin. the led pin is a programmable constant current sink. the boost converter will regulate its output to force the led pin to 300mv. the percentage of full-scale current sunk by the led pin is programmed via i 2 c. the led boost converter is designed for very high duty cycle operation and can boost from below 3 v to 40 v out at up to 55 ma. the led boost also features an overvolt- age protection feature to limit the output voltage in case of an open circuit in an led string. the boost converter will operate in either continuous conduction mode, dis- continuous conduction mode or pulse-skipping mode depending on the inductor current required for regulation . the boost converter may also be configured to operate as an independent high voltage boost regulator via i 2 c. the led driver may also be configured as a single string led driver. when driving a single string, led1 and led2 should be tied together. the led driver features a fully automatic gradation circuit . this circuit allows the current to ramp up or down at a controlled rate between any two current levels. on power- up the led dac register is set to 0. to enable the led driver a non-zero value must be programmed into this register.
LTC3675/LTC3675-1 19 36751fc for more information www.linear.com/LTC3675 o pera t ion the gradation circuit will then ramp the current to the programmed value at a rate determined by the gradation rate bits. once the led driver reaches this value it will regulate that current until programmed otherwise. if a new value is programmed in the led brightness register, the led drivers current will ramp up or down at the pro- grammed rate until that current is reached. to disable the led driver, a code of zero is programmed in the led dac register. the gradation circuit will then ramp the current down at the programmed rate. once the current reaches zero the gradation circuit will disable the boost and the entire led driver will enter shutdown mode. the led driver is protected by the led_ov pin. this pin acts as a secondary feedback path that limits the voltage on the output capacitor. a feedback divider is placed from the led boosts output to the led_ov pin. values for this divider are selected to limit the output voltage similarly to the feedback dividers discussed in switching regulator output voltage and feedback network in the applications information section. the led driver begins to transition to led_ov control at 800 mv and is fully controlled by the led_ov pin by 825 mv. during this transition the led pins will begin to drop out of regulation. for this reason during normal operation the voltage on this pin should be kept below 800mv. the led driver is also designed to limit the maximum voltage on the led1 and led2 pins to no more than 8v. the boost regulates the minimum voltage on either led pin. if one of the led pins is shorted to ground the boost will only drive the other led pin up to the voltage clamp, or the led_ov voltage, whichever is lower. if one led string is shorted, or partially shorted, this clamp will prevent the boost from damaging the led pin. p ushbut ton i nterf ace and p ower -u p p ower - d own s equencing the LTC3675/LTC3675-1 provide pushbutton functional- ity to either power up or power down the part. the onb, wake and pbstat pins provide the user with flexibility to power up or power down the part in addition to having i 2 c control. all pb timing parameters are scaled using the ct pin. times described below apply to a nominal c t of 0.01f. the ltc 3675/LTC3675-1 are in an off state when it is powered up with all regulators in shutdown. the wake pin is low in the off state. the wake pin will go high either if onb is pulled low for 400 ms or a regulator is enabled via its enable pin or an i 2 c command. the wake pin stays in its high state for 5 seconds and then gets pulled low. wake will not go high again if a second regulator is subsequently enabled. the LTC3675/LTC3675-1 are in an on state if either the wake pin is high or a regulator is enabled. the pbstat pin reflects the status of the onb when the LTC3675/LTC3675-1 are in an on state. once in the on state, the LTC3675/LTC3675-1 can be powered down by holding onb low for at least 5 seconds. all enabled regulators will be turned off for 1 second and the contents of the program registers are reset to their default state. this manner of power-down is called a hard reset. a hard reset may also be generated by using an i 2 c command. p ower -u p and p ower -d own via p ushbut ton the LTC3675/LTC3675-1 may be turned on and off using the wake pin as shown in figures 2 a and 2 b. in figures 2a and 2 b, pressing onb low at time t 1 , causes the wake pin to go high at time t 2 and stay high for 5 seconds, after which wake is pulled low. wake going high at t 2 causes buck regulator 1 to power up, which sequentially powers up the other buck regulators. the rstb pin gets pulled high 200 ms after the last enabled buck is in its pgood state. an application showing sequential regulator start- up is shown in the typical applications section (figure 7). if an i 2 c command is written before the 5 second wake period t 3 to keep the buck regulators enabled, the regula- tors stay enabled as shown in figure 2 b. otherwise, when wake gets pulled low at t 3 , the buck regulators will also power down sequentially as shown in figure 2a. in figure 2 b, onb is held low at instant t 4 for 5 seconds. this causes a hard reset to be generated and at t 5 , all regulators are powered down.
LTC3675/LTC3675-1 20 36751fc for more information www.linear.com/LTC3675 o pera t ion figure 2a. power-up using wake (sequenced power-up, figure 7) figure 2b. power-up using wake and power-down due to hard reset (sequenced power-up, figure 7) figure 2c. power-up using an enable pin and power-down due to i 2 c generated hard reset onb pbstat bucks 1?4 rstb wake sequence up t 2 t 1 t 3 t 4 t 5 5 sec 36751 f02b (buck regulator 1 is enabled via i 2 c, before t 3 ) onb (hi-z) pbstat (hi-z) buck 1 en1 rstb wake t 2 t 1 t 4 t 3 36751 f02c onb pbstat (hi-z) bucks 1?4 rstb wake (tied to en1) 5 sec t 2 t 1 sequence up sequence down (buck regulator?s enable is not reinforced by i 2 c before t 3 ) t 3 36751 f02a
LTC3675/LTC3675-1 21 36751fc for more information www.linear.com/LTC3675 o pera t ion p ower - u p and p ower - d own via e nable p in or i 2 c with the LTC3675/LTC3675-1 in its off state, a regulator can be enabled either via its enable pin or i 2 c. in figure 2 c, buck regulator 1 is enabled via its enable pin at time t 1 . the wake pin goes high for 5 seconds and at t 2 is pulled low. the buck regulator stays enabled until time t 3 when a hard reset command is issued via i 2 c. the buck regula- tor powers down and stays off for 1 second. at time t 4 , the LTC3675/LTC3675-1 exit from the power down state. since the buck regulator 1 is still enabled via its enable pin, it powers back up. wake also gets pulled high for 5 seconds. the rstb pin gets pulled high 200 ms after the buck regulator 1 is in its pgood state. led c urrent p rogramming the led current is primarily controlled through the led dac register at i 2 c sub- address 8. this register controls an 8 bit current dac. a 20 k resistor placed between the led_ fs pin and ground provides a current reference for the dac which results in 98 a of programmed led current per lsb. for example, programming a led dac register code of 64 h will result in a led current of 9.8ma and a full- scale setting of ffh will result in a led current of 25ma. the 2 xfs bit which is bit 3 of the led configuration register at sub-address 7 effectively doubles the programmed led current. with a 20 k resistor from led_fs to ground each lsb will be 196 a. programming a led dac register code of 64 h will result in a led current of 19.6 ma and a full-scale setting of ffh will result in an led current of 50ma. the 2 xfs mode is only intended for use when the output voltage is below 20v. i 2 c i nterface the LTC3675/LTC3675-1 may communicate with a bus master using the standard i 2 c 2- wire interface. the timing diagram (figure 3) shows the relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources, such as the ltc1694 smbus accelerator, are required on these lines. the LTC3675/LTC3675-1 are both a slave receiver and slave transmitter. the i 2 c control signals, sda and scl are scaled internally to the dv cc supply. dv cc should be connected to the same power supply as the bus pull-up resistors. the i 2 c port has an undervoltage lockout on the dv cc pin. when dv cc is below 1 v , the i 2 c serial port is cleared and the LTC3675/LTC3675-1 registers are set to their default configurations. i 2 c bus speed the i 2 c port is designed to be operated at speeds of up to 400 khz. it has built-in timing delays to ensure correct operation when addressed from an i 2 c compliant master device. it also contains input filters designed to suppress glitches should the bus become corrupted. figure 3. i 2 c bus operation t su, dat t hd, sta t hd, dat sda scl t su, sta t hd, sta t su, sto 36751 f03 t buf t low t high start condition repeated start condition stop condition start condition t r t f t sp ack ack 1 2 3 address wr 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 ack stop start sda scl data byte a data byte b
LTC3675/LTC3675-1 22 36751fc for more information www.linear.com/LTC3675 o pera t ion i 2 c start and stop conditions a bus master signals the beginning of communications by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high . the master may transmit either the slave write or the slave read address. once data is written to the LTC3675/LTC3675-1, the master may transmit a stop condition which commands the LTC3675/LTC3675-1 to act upon its new command set. a stop condition is sent by the master by transitioning sda from low to high while scl is high . the bus is then free for communication with another i 2 c device. i 2 c byte format each byte sent to or received from the LTC3675/ LTC3675-1 must be 8 bits long followed by an extra clock cycle for the acknowledge bit. the data should be sent to the LTC3675/ LTC3675-1 most significant bit (msb) first. i 2 c acknowledge the acknowledge signal is used for handshaking between the master and the slave. when the LTC3675/LTC3675-1 are written to ( write address), it acknowledges its write address as well as the subsequent two data bytes. when it is read from ( read address), the ltc 3675/LTC3675-1 acknowledge its read address only. the bus master should acknowledge receipt of information from the LTC3675/ LTC3675-1. an acknowledge ( active low) generated by the LTC3675/ LTC3675-1 lets the master know that the latest byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line ( high) during the acknowledge clock cycle. the LTC3675/LTC3675-1 pull down the sda line during the write acknowledge clock pulse so that it is a stable low during the high period of this clock pulse. when the LTC3675/LTC3675-1 are read from, it releases the sda line so that the master may acknowledge receipt of the data. since the LTC3675/LTC3675-1 only transmit one byte of data during a read cycle, a master not acknowl- edging the data sent by the LTC3675/LTC3675-1 has no i 2 c specific consequence on the operation of the i 2 c port. i 2 c slave address the LTC3675 responds to a 7- bit address which has been factory programmed to b0001001[r/wb]. the lsb of the address byte, known as the read/write bit, should be 0 when writing data to the LTC3675 and 1 when reading data from it. considering the address as an 8- bit word, the write address is 12 h and the read address is 13 h. the LTC3675-1 is factory programmed to b0110100[r/wb]. its write address is 68h and the read address is 69h. the LTC3675/LTC3675-1 will acknowledge both the read and write addresses. i 2 c sub-addressed writing the LTC3675/LTC3675-1 have twelve command registers for control input. they are accessed by the i 2 c port via a sub-addressed writing system. a single write cycle of the LTC3675/LTC3675-1 consists of exactly three bytes except when a clear interrupt command is written. the first byte is always the LTC3675/ LTC3675-1s write address. the second byte represents the sub- address . the sub-address is a pointer which directs the subsequent data byte within the LTC3675/LTC3675-1. the third byte consists of the data to be written to the location pointed to by the sub-address. the LTC3675/LTC3675-1 contain 11 control registers which can be written to. i 2 c bus write operation the master initiates communication with the LTC3675/ LTC3675-1 with a start condition and the appropriate write address. if the address matches that of the LTC3675/ LTC3675-1, the LTC3675/LTC3675-1 return an acknowl- edge. the master should then deliver the sub-address. again the LTC3675/ LTC3675-1 acknowledge and the cycle is repeated for the data byte. the data byte is transferred to an internal holding latch upon the return of its acknowl- edge by the LTC3675/LTC3675-1. this procedure must be repeated for each sub-address that requires new data. after one or more cycles of [address][sub-address] [ data ], the master may terminate the communication with a stop condition. multiple sub addresses may be written to with a single address command using a
LTC3675/LTC3675-1 23 36751fc for more information www.linear.com/LTC3675 o pera t ion table 1. summary of i 2 c sub-addresses and byte formats. bits a7, a6, a5, a4 of sub-address need to be 0 to access registers sub-address a7a6a5a4a3a2a1a0 oper- ation action byte format d7d6d5d4d3d2d1d0 default d7d6d5d4d3d2d1d0 comments 0000 0000 (00h) write no register selected used in the clear interrupt operation. 0000 0001 (01h) read/ write buck1 register enable, out_hi-z, mode, slow, dac[3], dac[2], dac[1], dac[0] 01101111 0000 0010 (02h) read/ write buck2 register enable, out_hi-z, mode, slow, dac[3], dac[2], dac[1], dac[0] 01101111 0000 0011 (03h) read/ write buck3 register enable, out_hi-z, mode, slow, dac[3], dac[2], dac[1], dac[0] 01101111 0000 0100 (04h) read/ write buck4 register enable, out_hi-z, mode, slow, dac[3], dac[2], dac[1], dac[0] 01101111 0000 0101 (05h) read/ write boost register enable, unused, mode, slow, dac[3], dac[2], dac[1], dac[0] 00001111 0000 0110 (06h) read/ write buck-boost register enable, unused, mode, slow, dac[3], dac[2], dac[1], dac[0] 00001111 0000 0111 (07h) read/ write led configuration register unused, mode[1], mode[0], slow, 2xfs, grad[2], grad[1], grad[0] 00001111 0000 1000 (08h) read/ write led dac register dac[7], dac[6], dac[5], dac[4], dac[3], dac[2], dac[1], dac[0] 00000000 00000000 = led driver disabled 11111111 = 25ma per string 0000 1001 (09h) read/ write uvot register reset_all, uv[2], uv[1], uv[0], unused, unused , ot[1], ot[0] 00000000 0000 1010 (0ah) read/ write rstb mask register unused, pgood[7], pgood[6], pgood[5], pgood[4], pgood[3], pgood[2], pgood[1] 11111111 fault will pull rstb low if the corresponding bit is 1 0000 1011 (0bh) read/ write irqb mask register unused, pgood[7], pgood[6], pgood[5], pgood[4], pgood[3], pgood[2], pgood[1] 00000000 fault will pull irqb low if the corresponding bit is 1 0000 1100 (0ch) read status register (real time) unused, unused, pgood[6], pgood[5], pgood[4], pgood[3], pgood[2], pgood[1] read back 0000 1101 (0dh) read status register (latched) uv, ot, pgood[6], pgood[5], pgood[4], pgood[3], pgood[2], pgood[1] read back 0000 1111 (0fh) write clear interrupt clears the interrupt bit, status latches are unlatched [ address][sub- address][ data ][sub- address] [ data ] sequence. alternatively, a repeat - start condition can be initiated by the master and another chip on the i 2 c bus can be addressed. this cycle can continue indefinitely and the LTC3675/LTC3675-1 will remember the last input of valid data that it received. once all chips on the bus have been addressed and sent valid data, a global stop can be sent and the LTC3675/LTC3675-1 will update its command latches with the data that it had received. it is important to understand that until a stop signal is transmitted, data written to the ltc 3675/LTC3675-1 command registers are not acted on by the LTC3675/ LTC3675-1. only once a stop signal is issued is the data transferred to the command latch and acted on. the one exception is when sub-address 0 fh is written to clear an interrupt. to clear an interrupt, sub address ofh must be written, followed by sub address 00 h. a complete clear interrupt cycle would have the following write sequence: 12h, 0fh, stop, 12h, 00h, stop. i 2 c bus read operation the LTC3675/LTC3675-1 have eleven command registers and two status registers. the contents of any of these registers may be read back via i 2 c. to read the data of a register, that registers sub-address must be provided to the LTC3675/LTC3675-1. the bus master reads the status of the LTC3675/LTC3675-1 with a start condition followed by the LTC3675/LTC3675-1s write address followed by the first data byte ( the sub- address of the register whose data needs to be read) which
LTC3675/LTC3675-1 24 36751fc for more information www.linear.com/LTC3675 o pera t ion is acknowledged by the LTC3675/ LTC3675-1. after receiv- ing the acknowledge signal from the LTC3675/LTC3675-1 the bus master initiates a new start condition followed by the LTC3675/LTC3675-1 read address. the LTC3675/ LTC3675-1 acknowledge the read address and then return a byte of read back data from the selected register. a stop command is not required for the bus read operation. immediately after writing data to a register, the contents of that register may be read back if the bus master issues a start condition followed by the LTC3675/LTC3675-1 read address. e rror c ondition r epor ting via rstb and irqb p ins error conditions are reported back via the irqb and rstb pins. after an error condition is detected, status data can be read back to a microprocessor via i 2 c to determine the exact nature of the error condition. figure 4 is a simplified schematic showing the signal path for reporting errors via the rstb and irqb pins. all the switching regulators and the led driver have an internal power good ( pgood) signal. when the regulated output voltage of an enabled switcher rises above 93.5% of its programmed value, the pgood signal will transition high. when the regulated output voltage falls below 92.5% of its programmed value, the pgood signal is pulled low. if that pgood is not masked and stays low for greater than 50s, then it pulls the rstb and irqb pins low, indicating to a microprocessor that an error condition has occurred. the 50 s filter time prevents the pins from being pulled low due to a transient. the led driver has a pgood signal ( pgood[7]) that is used to indicate output voltage status only when it is configured as a high voltage boost regulator. in all other operating modes, pgood[7] is disabled. an error condition that pulls the rstb pin low is not latched. when the error condition goes away, the rstb pin is released and is pulled high if no other error condi- tion exists. in addition to the pgood signals of the regulators, the irqb pin also indicates the status of the overtemperature figure 4. simplified schematic showing rstb and irqb signal path 36751 f04 rstb mask register pgood comparator v out irqb mask register regulator 92% of programmed v out other unmasked pgood outputs unmasked pgood outputs unmasked error external pull-up resistor v in + ? and1 and2 other unmasked errors real time status register latched status register set clr clrint external pull-up resistor irqb rstb v in
LTC3675/LTC3675-1 25 36751fc for more information www.linear.com/LTC3675 and undervoltage flags. the undervoltage and overtem- perature faults cannot be masked. a fault that causes the irqb pin to be pulled low is latched. when the fault condition is cleared, the irqb pin is still maintained in its low state. the user needs to clear the interrupt by using a clrint command. on start- up, all pgood outputs are unmasked and a power- on reset will cause rstb to be pulled low. once all enabled regulators have their output pgood for 200 ms typical (c t = 0.01f) the rstb output goes hi-z. by masking a pgood signal, the rstb or irqb pin will remain hi-z even though the output voltage of a regulator may be below its pgood threshold. however, when the status register is read back, the true condition of pgood is reported. u nder voltage and o ver temperature f unctionalit y the undervoltage ( uv) circuit monitors the input sup- ply voltage and shuts down all enabled regulators if the input voltage falls below 2.45 v. the LTC3675/LTC3675-1 also provide a user with an undervoltage warning, which indicates to the user that the input supply voltage is ap- proaching the uv threshold. the undervoltage warning threshold is user programmable as shown in table 2. table 2. uv warning thresholds uv[2], uv[1], uv[0] falling v in warning threshold 000 (default) 2.7v 001 2.8v 010 2.9v 011 3.0v 100 3.1v 101 3.2v 110 3.3v 111 3.4v to prevent thermal damage to the LTC3675/LTC3675-1 and its surrounding components, the LTC3675/ LTC3675-1 incorporate an overtemperature ( ot) function. when the die temperature reaches 150 c all enabled regulators are shut down and remain in shutdown until the die tempera- ture falls to 135 c. the LTC3675/LTC3675-1 also have an overtemperature warning function which warns a user that the die temperature is approaching the ot threshold which allows the user to take any corrective action. the ot warning threshold is user programmable as shown in table 3. table 3. ot warning thresholds ot[1], ot[0] ot warning threshold 00 (default) 10 below ot 01 20 below ot 10 30 below ot 11 40 below ot a uv or ot warning is reported to the user when the irqb pin is in its high impedance state. the uv and ot warning flags are not maskable by the user. reset_ all functionality: the reset_ all bit shuts down all enabled regulators ( enabled either via its enable pin or i 2 c) for 1 second. all command registers are cleared and put in their default state. o pera t ion
LTC3675/LTC3675-1 26 36751fc for more information www.linear.com/LTC3675 table 4. recommended inductors for 1a buck regulators and ganged buck 3, buck 4 application part number l(h) max i dc (a) max dcr (m) size in mm (l w h) manufacturer lps4018-222 2.2 2.8 70 4 4 1.8 coilcraft www.coilcraft.com xfl4022-222 2.2 3.5 21.35 4 4 2 coilcraft www.coilcraft.com lt f 5022-2r2 2.2 3.2 36 5 5.2 2.2 tdk www.tdk.com lps3015-222 2.2 2.0 110 3 3 1.5 coilcraft www.coilcraft.com table 5. recommended inductors for 500ma buck regulators part number l(h) max i dc (a) max dcr (m) size in mm (l w h) manufacturer lps3015-222 2.2 2.0 110 3 3 1.5 coilcraft www.coilcraft.com mlps3015-2r2 2.2 1.4 110 3 3 1.5 maglayers www.maglayers.com mdt2520-cr2r2 2.2 1.35 90 2.5 2 1 toko www.toko.com lqm2hpn2r2 2.2 1.0 120 2.5 2 1.1 murata www.murata.com switching regulator output voltage and feedback network the output voltage of the switching regulators is pro- grammed by a resistor divider connected from the switching regulators output to its feedback pin and is given by v out = v fb (1 + r2/r1) as shown in figure 5. typical values for r1 range from 40 k to 1 m. the buck regulator transient response may improve with optional capacitor c ff that helps cancel the pole created by the feedback resistors and the input capacitance of the fb pin. experimentation with capacitor values between 2 pf and 22 pf may improve transient response. a pplica t ions i n f or m a t ion figure 5. feedback components buck regulators all four buck regulators are designed to be used with 2.2h inductors. tables 4 and 5 show the recommended inductors for the 500ma and 1a buck regulators. the input supply needs to be decoupled with a 10f capacitor while the output needs to be decoupled with a 22 f capacitor for a 1 a buck regulator and 10 f for a 500ma buck regulator. refer to capacitor selection in the applications information section for details on selecting a proper capacitor. each buck regulator can be programmed via i 2 c . to program buck regulator 1 (1a ) use sub- address 01h , buck regulator 2 (1a) sub-address 02 h, buck regulator 3 (500 ma) sub- address 03 h and buck regulator4 (500 ma) sub-address 04h. the bit format is explained in table 6. combined buck regulators a single 2 a buck regulator is available by combining both 1a buck regulators together. both the 500ma buck regula- tors may also be combined together to form a 1 a buck regulator. tables 4 and 7 show the recommended inductors. the input supply needs to be decoupled with a 22f capacitor while the output needs to be decoupled with switching regulator (buck, boost, buck-boost) v out c out (optional) c ff r2 r1 fb 36751 f05 +
LTC3675/LTC3675-1 27 36751fc for more information www.linear.com/LTC3675 a pplica t ions i n f or m a t ion table 7. recommended inductors for 2a combined buck regulator part number l(h) max i dc (a) max dcr (m) size in mm (l w h) manufacturer xfl4022-222 2.2 3.5 21.35 4 4 2 coilcraft www.coilcraft.com lps6225-222 2.2 4 45 6 6 2.5 coilcraft www.coilcraft.com fdv0530-2r2 2.2 5.3 17.3 6.2 5.8 3 toko www.toko.com table 6. buck regulator program register bit format bit7 enable default is 0 which disables the part. a buck regulator can also be enabled via its enable pin. when enabled via pin, the contents of the i 2 c register program its functionality. bit6 out_hi-z default is 1 in which the sw node remains in a high impedance state when the regulator is in shutdown. a 0 pulls the sw node to gnd through a 10k resistor. bit5 mode default is 1 which is burst mode operation. a 0 programs the regulator to operate in pulse-skipping mode. bit4 slow edge this bit controls the slew rate of the switch node. default is 0 which enables the switch node to slew at a faster rate, than if the bit were programmed a 1. bit3(dac3) bit2(dac2) bit1(dac1) bit0(dac0) dac control these bits are used to program the feedback regulation voltage. default is 1111 which programs a full-scale voltage of 800mv. bits 0000 program the lowest feedback regulation of 425mv. a lsb (dac0) has a bit weight of 25mv. table 8. recommended inductors for boost regulator and buck-boost regulator part number l(h) max i dc (a) max dcr (m) size in mm (l w h) manufacturer xfl4022-222 2.2 3.5 21.35 4 4 2 coilcraft www.coilcraft.com lt f 5022-2r2 2.2 3.2 36 5 5.2 2.2 tdk www.tdk.com table 9. boost regulator program register bit format bit7 enable default is 0 which disables the boost. bit6 x unused bit5 mode mode = 0 is pwm mode, mode = 1 is burst mode operation bit4 slow edge this bit controls the slew rate of the switch node. default is 0 which enables the switch node to slew at a faster rate than if the bit were programmed a 1. bit3(dac3) bit2(dac2) bit1(dac1) bit0(dac0) dac control these bits are used to program the feedback regulation voltage. default is 1111 which programs a full-scale voltage of 800mv. bits 0000 program the lowest feedback regulation of 425mv. a lsb (dac0) has a bit weight of 25mv. a 47 f capacitor for a 2 a combined buck regulator and 22f for a 1 a combined buck regulator. refer to capaci- tor selection in the applications information section for details on selecting a proper capacitor. boost regulator the boost regulator is designed to be used with a 2.2h inductor. table 8 provides a list of recommended inductors. the input supply needs to be decoupled with a 10f capacitor while the output needs to be decoupled with two 22 f capacitors. refer to capacitor selection in the applications information section for details on selecting a proper capacitor . the boost regulator can be programmed via i 2 c. to pro- gram the boost regulator, use sub-address 05 h. the bit format is explained in table 9.
LTC3675/LTC3675-1 28 36751fc for more information www.linear.com/LTC3675 a pplica t ions i n f or m a t ion optional capacitor c ff is not needed and may compromise loop stability. buck-boost regulator the buck-boost regulator is an internally compensated voltage mode regulator that is designed to be used with a 2.2 h inductor. recommended inductors are listed in the table 8. the input supply needs to be decoupled with a 10f capacitor while the output needs to be decoupled with a 22 f capacitor. refer to capacitor selection in the applications information section for details on selecting a proper capacitor. the buck-boost regulator can be programmed via i 2 c. to program the buck-boost regulator, use sub-address 06h. the bit format is explained in table 10. to ensure loop stability, feedback resistor r1 in figure 5 should be no greater than 105 k. optional capacitor c ff is not needed and may compromise loop stability. led driver for proper operation the led driver boost circuit needs a 10 h inductor. recommended inductors are listed in table 11. the led driver also needs a rectifier diode. recommended schottky diodes are listed in table 12. the led driver has two registers that can be programmed via i 2 c. one of the registers is accessed at sub-address 07h and the bit format is as shown in table 13. the rate at which the gradation circuit ramps the led cur- rent is set by grad[2:0]. grad[2:0] sets the time the led driver will take to transition through one lsb of led current . table 10. buck-boost regulator program register bit format bit7 enable default is 0 which disables the buck-boost. the buck-boost regulator can alternately be enabled via its enable pin. when enabled via pin, the contents of the i 2 c register program its functionality. bit6 x unused bit5 mode mode = 0 is pwm mode, mode = 1 is burst mode operation. default is 0. bit4 slow edge this bit controls the slew rate of the switch node. default is 0 which enables the switch node to slew at a faster rate than if the bit were programmed a 1. bit3(dac3) bit2(dac2) bit1(dac1) bit0(dac0) dac control these bits are used to program the feedback regulation voltage. default is 1111 which programs a full-scale voltage of 800mv. bits 0000 program the lowest feedback regulation of 425mv. a lsb (dac0) has a bit weight of 25mv. table 11. recommended inductors for led driver part number l(h) max i dc (a) max dcr (m) size in mm (l w h) manufacturer lps6225-103m 10 2.1 105 6 6 2.5 coilcraft www.coilcraft.com ihlp2020bzer10rm01 10 4 184 5.2 5.5 2 vishay www.vishay.com table 12. recommended schottky diodes for led driver part number i f (a) manufacturer pd3s140 1.0 diodes inc. www.diodes.com zlls1000 1.16 diodes inc./zetex www.diodes.com ctlsh1-40m322 1.0 central semiconductor www.centralsemi.com
LTC3675/LTC3675-1 29 36751fc for more information www.linear.com/LTC3675 table 13. led driver regulator program register 1 bit format bit7 x unused bit6 bit5 mode1 mode0 mode1 = mode0 = 0 is default; both led pins are regulated. mode1 = 0 mode0 = 1; only led1 is regulated. (single string application). mode1 = 1 mode0 = 0; led driver is configured as a high voltage boost regulator. mode1 = mode0 = 1; both led pins are regulated, but boost is not powered up. in this mode an external voltage is needed to drive the leds. bit4 slow edge this bit controls the slew rate of the switch node. default is 0 which enables the switch node to slew at a faster rate than if the bit were programmed a 1. bit3 2xfs this bit doubles the full-scale programmed led current. default is 1. bit2(grad2) bit1(grad1) bit0(grad0) dac control led current gradation timing bits. default is 111. see table 14. a pplica t ions i n f or m a t ion these times are shown in table 14. the default state of 000 in grad[2:0] results in a very fast ramp time that cannot be visually perceived. table 14. led gradation bits grad2, grad1, grad0 gradation step time 000 0.056 ms 001 0.912 ms 010 1.824 ms 011 3.648 ms 100 7.296 ms 101 14.592 ms 110 29.184 ms 111 (default) 58.368 ms the led dac register is at sub-address 08 h. all 8 bits in this register are used to control led current. the default state of this register is 00 h which disables the led driver. see table 1. operating the led driver as a high voltage boost regulator the led driver may be configured as a high voltage boost regulator capable of producing an output voltage up to 40v. the boost mode may be programmed via i 2 c. in this mode, the led_ov pin serves as the feedback pin. the feedback resistors are selected as discussed in the switching regulator output voltage and feedback network section. the led_fs pins must be tied to the input supply in this mode. when configured as a high voltage boost, the led dac register is ignored. to maintain stability, the average inductor current must be maintained below 750 ma. this limits the deliverable output current at low input supply voltages. figure 8 gives an example of the led driver configured as a high voltage boost regulator. input and output decoupling capacitor selection the LTC3675/LTC3675 -1 have multiple input supply pins and output pins. each of these pins must be decoupled with low esr capacitors to gnd. these capacitors must be placed as close to the pins as possible. ceramic dielectric capacitors are a good compromise between high dielectric constant and stability versus temperature and dc bias. note that the capacitance of a capacitor deteriorates at higher dc bias. it is important to consult manufacturer data sheets and obtain the true capacitance of a capacitor at the dc bias voltage it will be operated at. for this rea- son, avoid the use of y5v dielectric capacitors. the x5r/ x7r dielectric capacitors offer good overall performance. the input supply voltage pins 6, 7, 10 and 40 all need to be decoupled with at least 10 f capacitors. the input supply pins 31 and 34 and the dvcc pin 41 need to be decoupled with 2.2 f capacitors. the outputs of the 1a buck regulators need 22 f capacitors, while the outputs of the 500 ma buck regulators need 10 f capacitors. the buck-boost output regulator needs a 22 f decoupling capacitor. the boost regulator needs two 22 f output decoupling capacitors. the led driver output pin should be decoupled with a 4.7f capacitor.
LTC3675/LTC3675-1 30 36751fc for more information www.linear.com/LTC3675 a pplica t ions i n f or m a t ion choosing the c t capacitor the c t capacitor may be used to program the timing parameters associated with the pushbutton. for a given c t capacitor the timing parameters may be calculated as below. c t is in units of f. t onb_lo = 5000 c t ms t pbstat_pw = 5000 c t ms t onb_wake = 40000 c t ms t wake_on = 500 c t seconds t onb_hr = 500 c t seconds t hr = 100 c t seconds programming the uvot register the uv/ot warning byte (default 0000 0000) structure is as below: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset_all uv[2] uv[1] uv[0] unused unused ot[1] ot[0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 unused pgood7 pgood6 pgood5 pgood4 pgood3 pgood2 pgood1 programming the rstb and irqb mask registers the rstb mask register can be programmed by the user at sub-address 0ah and its format is as below. if a bit is set to 1, then the corresponding regulators pgood will pull rstb low if a pgood fault were to occur. the default for this register is ffh. the irqb mask register has the same bit format as the rstb mask register. the irqb mask register is located at sub-address 0bh and its default contents are 00h. pgood7 is used only when the led driver is configured as a high voltage boost regulator.
LTC3675/LTC3675-1 31 36751fc for more information www.linear.com/LTC3675 a pplica t ions i n f or m a t ion status byte read back when either the rstb or irqb pin is pulled low, it indicates to the user that a fault condition has occurred. to find out the exact nature of the fault, the user can read the status reg- isters. there are two status registers. one register provides real time fault condition reporting while a second register latches data when an interrupt has occurred. figure 4 shows the operation of the real time and latched status registers. the contents of the latched status register are cleared when a clrint signal is issued. a pgood bit is a 0 if that regulators output voltage is more than 8% below its programmed value. the sub-address for the real time status register is 0ch and its format is as follows: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 unused unused pgood6 pgood5 pgood4 pgood3 pgood2 pgood1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 uv ot pgood6 pgood5 pgood4 pgood3 pgood2 pgood1 the sub-address for the latched status register is 0 dh and its format is as follows: a write operation cannot be performed to either of the status registers. pcb considerations when laying out the printed circuit board, the following list should be followed to ensure proper operation of the LTC3675/LTC3675-1: 1. the exposed pad of the package ( pin 45) should connect directly to a large ground plane to minimize thermal and electrical impedance. 2. all the input supply pins must be tied together and each supply pin should have a decoupling capacitor. 3. the switching regulator input supply pins and their re- spective decoupling capacitors should be kept as short as possible. the gnd side of these capacitors should
LTC3675/LTC3675-1 32 36751fc for more information www.linear.com/LTC3675 connect directly to the ground plane of the part. these capacitors provide the ac current to the internal power mosfets and their drivers. its important to minimize inductance from these capacitors to the v in pins of the LTC3675/LTC3675-1. 4. the switching power traces connecting sw1, sw2, sw3, sw4, sw5, swab6, swcd6 and sw7 to their respective inductors should be minimized to reduce radiated emi and parasitic coupling. due to the large voltage swing of the switching nodes, high input impedance sensitive nodes such as the feedback nodes and led_ov node should be kept far away or shielded from the switching nodes or poor performance could result. 5. the gnd side of the switching regulator output capaci- tors should connect directly to the thermal ground plane of the part. minimize the trace length from the output capacitor to the inductor(s)/pin(s). 6. in a combined buck regulator application the trace length of switch nodes to the inductor must be kept equal to ensure proper operation. a pplica t ions i n f or m a t ion
LTC3675/LTC3675-1 33 36751fc for more information www.linear.com/LTC3675 typical a pplica t ions figure 6. detailed front page application circuit LTC3675/ LTC3675-1 exposed pad 2.2h 2.2h 2.2h 2.2h 0.01f i 2 c control microprocessor control push button ? ? ? v in ldo_out ldofb v in sw5 vout5 fb5 swab6 swcd6 vout6 fb6 dv cc scl sda irqb rstb wake pbstat en1 en2 en3 en4 en6 ct onb v in sw1 fb1 v in sw2 fb2 v in sw3 fb3 sw4 fb4 sw7 led1 led2 led_ov led_fs 36751 f06 ? ? ? up to 10 leds 324k 649k 324k 649k 2.2f li-ion cell 2.7v to 4.2v 655k 2.5v 1a 309k 1.2v 1a 1.2v 25ma 1.05m 200k 2.2h 5v, 1a 3.3v, 1a 590k 1.8v 500ma 475k 10f 4.7f 50v 511k 1.6v 500ma 511k 10h 1f 322k 105k 10f 22f 22f 2.2h 1.96m 42.2k 20k 10f 22f 10f 10f 22f 22f 10f 10f 10f 10f
LTC3675/LTC3675-1 34 36751fc for more information www.linear.com/LTC3675 typical a pplica t ions figure 7. buck regulators with sequenced start-up and a single string of leds. buck regulators power-up in the sequence buck1, buck2 and buck3 LTC3675/ LTC3675-1 exposed pad 2.2h 2.2h 2.2h 2.2h 0.01f i 2 c control microprocessor control push button ? ? ? v in ldo_out ldofb v in sw5 vout5 fb5 swab6 swcd6 vout6 fb6 dv cc scl sda irqb rstb wake pbstat en1 en2 en3 en4 enbb ct onb v in sw1 fb1 v in sw2 fb2 v in sw3 fb3 sw4 fb4 sw7 led1 led2 led_ov led_fs 36751 f07 up to 10 leds 324k 649k 324k 649k 10f 2.2f li-ion cell 2.7v to 4.2v 2.2h 655k 2.5v 1a 309k 1.2v 1a 1.2v 25ma 1.05m 200k 2.2h 5v, 1a 3.3v, 1a 590k 1.8v 500ma 475k 4.7f 50v 511k 1.6v 500ma 511k 10h 1f 332k 105k 10f 1.96m 42.2k 20k 10f 22f 10f 22f 22f 10f 10f 22f 22f 10f 10f 10f
LTC3675/LTC3675-1 35 36751fc for more information www.linear.com/LTC3675 typical a pplica t ions figure 8. combined buck regulators and a high voltage boost regulator LTC3675/ LTC3675-1 exposed pad 2.2h 2.2h 0.01f i 2 c control microprocessor control push button v in ldo_out ldofb v in sw5 vout5 fb5 swab6 swcd6 vout6 fb6 dv cc scl sda irqb rstb wake pbstat en1 en3 enbb en2 en4 ct onb v in sw1 sw2 fb1 v in fb2 v in sw3 sw4 fb3 fb4 led_fs sw7 led_ov led1 led2 36751 f08 655k 309k 324k 649k 10f li-ion cell 2.7v to 4.2v 2.5v 2a 1.2v 25ma 1.05m 200k 2.2h 5v, 1a 3.3v, 1a 22f 324k 1.2v 1a 649k 12v 150ma 10f 20v 10h 1f 332k 105k 10f 2.2h 1.87m 133k 10f 22f 22f 10f 10f 10f 22f 22f 22f 2.2f 10f
LTC3675/LTC3675-1 36 36751fc for more information www.linear.com/LTC3675 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 5.60 ref 6.10 0.05 2.56 0.05 2.64 0.05 1.70 0.05 7.50 0.05 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 43 1 2 44 bottom view?exposed pad 2.40 ref 3.10 0.05 4.50 0.05 7.00 0.10 5.60 ref 0.75 0.05 0.20 0.05 (uff44ma) qfn rev a 0410 0.40 bsc 0.98 0.10 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 2.40 ref 2.64 0.10 0.40 0.10 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer uff package variation: uff44ma 44-lead plastic qfn (4mm 7mm) (reference ltc dwg # 05-08-1762 rev a) 2.56 0.10 1.70 0.10 2.76 0.10 0.74 0.10 r = 0.10 typ r = 0.10 typ r = 0.10 typ 0.74 0.10 0.40 bsc package outline 0.20 0.05 2.02 0.05 2.76 0.05 0.98 0.05 1.48 0.05 0.70 0.05
LTC3675/LTC3675-1 37 36751fc for more information www.linear.com/LTC3675 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 4/12 clarified pgood threshold voltage spec, added min/max clarified note 2, electrical grades and temperatures modified pin function descriptions for rstb and irqb changed figure reference in i 2 c interface section modified pgood comparator polarity figure 4 modified programming the rstb and irqb mask registers section modified status byte read back section modified application circuit v in caps 4 7 14 21 24 30 31 33, 34, 35, 38 b 10/12 added part number LTC3675-1 added new i 2 c address clarified maximum ambient temperature in note 2 1 - 38 6, 21-23 7 c 3/13 clarified en pin operation clarified buck-boost en pin operation modified figure 1 master-slave bucks and operation modified figure 8 14 15 17 to 18 35
LTC3675/LTC3675-1 38 36751fc for more information www.linear.com/LTC3675 ? linear technology corporation 2010 lt 0313 rev c ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC3675 r ela t e d p ar t s part number description comments ltc3569 triple buck regulator with 1.2a and tw o 600ma outputs and individual programmable references triple, synchronous, 100% duty cycle, pgood pin, programmable v fb servo voltage ltc3577/ ltc3577-1/ ltc3577-3/ ltc3577-4 highly integrated portable/navigation pmic pmic: linear power manager and three buck regulators, 10-led boost regulator, synchronous bucks adj at 800ma/500ma/500ma, pb control, i 2 c interface, 2 150ma ldos, ovp charge current programmable up to 1.5a from wall adapter input, thermal regulation, 4mm 7mm qfn-44 package; "-1" and "-4" versions have 4.1v v float , "-3" version for sirf atlas iv processors ltc3586/ ltc3586-1 switching usb power manager with li-ion/ polymer charger, 1a buck-boost + dual sync buck converter + boost + ldo pmic: switching power manager, 1a buck-boost + 2 bucks adj to 0.8v at 400ma/400ma + 800ma boost + ldo, charge current programmable up to 1.5a from wall adapter input, 4mm 6mm qfn-38 package; "-1" version has 4.1v v float typical a pplica t ion LTC3675/ LTC3675-1 exposed pad 2.2h 2.2h 2.2h 2.2h 0.01f i 2 c control microprocessor control push button ? ? ? v in ldo_out ldofb v in sw5 vout5 fb5 swab6 swcd6 vout6 fb6 dv cc scl sda irqb rstb wake pbstat en1 en2 en3 en4 en6 ct onb v in sw1 fb1 v in sw2 fb2 v in sw3 fb3 sw4 fb4 sw7 led1 led2 led_ov led_fs 36751 ta02 ? ? ? up to 10 leds 324k 649k 324k 649k 2.2f li-ion cell 2.7v to 4.2v 655k 2.5v 1a 309k 1.2v 1a 1.2v 25ma 1.05m 200k 2.2h 5v, 1a 3.3v, 1a 590k 1.8v 500ma 475k 10f 4.7f 50v 511k 1.6v 500ma 511k 10h 1f 332k 105k 10f 22f 2.2h 1.96m 42.2k 20k 10f 22f 10f 22f 10f 10f 22f 22f 10f 10f 10f

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